In the field of integrated circuit (IC) devices, several semiconductor die (commonly referred to as “chips”) can be combined into a single protective package. In some applications, such as that disclosed in U.S. patent application Ser. No. 09/666,208 filed on Dec. 21, 2000, entitled “Chip Testing Within a Multi-Chip Semiconductor Package,” which is assigned to the same assignee and incorporated by reference herein, a memory chip can be combined with a larger chip to provide both the functions of processing and storage of data. In such a combination, the number of external pins available for interacting with the logic or memory chips may be less than that which would be used if the two chips were packaged separately. Accordingly, there is a reduction in the overall number of external pins available for access to and from the chips.
It is important that packaged semiconductor devices be tested for quality before such devices are made available or sold to a customer. In the situation of multiple chips incorporated into a single package, testing can be made more complex if there is a reduction in the overall number of external pins. This is because many signals conveying patterns and addresses for use in testing are typically applied through external pins.